The present invention relates generally to memory devices and, more particularly, to an apparatus and method for low power sensing in a multi-port SRAM using pre-discharged bit lines.
A typical static random access memory (SRAM) cell includes an array (rows, columns) of individual SRAM cells. Each SRAM cell is capable of storing a voltage value therein, which voltage value represents a corresponding binary logical data bit value (e.g., a “low” or “0” value, and a “high” or “1” value). One existing configuration for an SRAM cell includes a pair of cross-coupled devices such as inverters. Using CMOS (complementary metal oxide semiconductor) technology, each inverter comprises a pull-up PFET (p-channel) transistor connected to a complementary pull-down NFET (n-channel) transistor, with the two transistors in each inverter typically connected in series between a positive voltage potential and ground. The inverters, further connected in a cross-coupled configuration, act as a bistable latch that stores the data bit therein so long as power is supplied to the memory array.
The transistors within the typical SRAM cell exhibit relatively significant current leakage, particularly at the word-line transistor gates and the bit-line transistor gates. Since known SRAM cell designs require a constant power level both to maintain the data bit stored in the SRAM latch and to allow the reading from and the writing to of data, the current leakage increases the power used by the array of SRAM cells. For example, one common technique is to continuously pre-charge all of the read bit lines within the SRAM to a logical high level; that is, to a positive voltage of, e.g., +1 volts. This is done when the bit lines are not being accessed. After a read cycle involving certain read bit lines, those bit lines are returned to their pre-charge state. The resulting undesirable use of power in these prior art designs increases with the increase in SRAM cell density and the overall number of cells on an integrated circuit (IC), such as a stand-alone memory device, or as part of a processor or application-specific integrated circuit (ASIC).
Various techniques to reduce the leakage current have been proposed, such as increasing the size of the cell by making the devices longer, increasing the threshold voltages of the cell, adding additional transistors to the cell, or lowering the voltage to the array when the cell is not being accessed. However, all of these techniques can increase the area of the array, or significantly reduce the performance of the array.
What is needed is an apparatus and method to reduce the DC power consumption in a multi-port SRAM cell due to relatively large cell current leakage as well as to reduce the AC power consumption in the multi-port SRAM cell due to relatively large read bit line voltage swings.